Conference Schedule

9:00-9:30 Registration and Refreshments

9:30-10:30 Keynote Speech (Prof. Ian Phillips) - "Making Molehills of Mountains"

10:30-10:45 Refreshments (Posters)

10:45-12:00 Paper Presentations (x 3)

12:00-13:00 LUNCH

13:00-13:50 Paper Presentations (x 2)

13:50-14:15 Refreshments (Posters and Voting for best paper and poster of the conference)

14:15-15:15 Discussion Panel

15:15-15:30 Best Paper / Poster winners presentation

15:30-15:45 Conference Delegate photo and closing announcement

15:45 Conference Close

Keynote Speech

Making a Mole-Hill out of a Mountain

Today we are already designing integrated circuits with more than a Billion transistors; and despite the faltering steps of Moore's law, we will be designing more than 10 times that within the next 5yrs. Yet even using High Level Description Languages (HDLs) with Synthesis, designer productivity still only delivers the low thousands of gates per day. How does industry ever deliver a complete design in a reasonable time-frame today? The answer is Reuse and Hierarchy. You don't design everything from scratch, but strive to use as much as possible of 'the last' design in the next. If you can hit 99%, then the 1B transistor opportunity, becomes a 10M transistor challenge ... still a large number, but much more manageable. Reuse is an indispensible part of product design today, yet seldom gets the academic attention it deserves. This talk will examine reuse today and its role in the pragmatic delivery of Electronic System products in the near and not-so-near future.